1. Field of the Invention
The present invention generally relates to a data processor, and more particularly to a data processor with an external bus interface.
2. Description of the Related Art
With diversification of systems using a data processor, a wide variety of equipment has been developed and produced as external devices for use around (or connected to) the data processor. These devices are typically referred to as "peripherals".
The bus interface for these sets of external devices is either a separate bus interface or a multiplexed bus interface which is used due to the limited number of terminals typically provided on the bus interface.
In a conventional data processor, typically only one type of bus interface is available, that is, either a separate (dedicated)-type or a multiplex-type. Therefore, if a bus conversion circuit is not used between a data processor and external equipment, a single data processor is unable to use an external device equipped with the other type of bus interface. Hereinbelow, a separate bus interface and a multiplex bus interface for the external bus interface of the conventional data processor, are described.
First, a conventional data processor having a separate bus interface circuit, includes at least a bus control unit (BCU) which controls the output and input of data and an execution unit (EXU) which controls execution of instructions, arithmetic operations, etc. The EXU also performs the writing of data to external equipment and the reading of data from the external equipment.
In the conventional data processor, the internal data signal of the BCU has an 8-bit width and the internal address width is assumed to be 16 bits. In the BCU, a first bus is an 8-bit (D0 through D7) data bus, a second bus is a low-order 8-bit (A0 through A7) address bus, and a third bus is a high-order 8-bit (A8 through A15) address bus. These first through third buses are connected to the EXU. Additionally, the first bus is connected to a data signal terminal, the second bus is connected to an address signal terminal, and the third bus is connected to an address signal terminal.
The operation of the conventional data processor is described hereinafter (as shown FIG. 2). First, time intervals T1-T4 indicate the timing of a clock (A) at which the data processor is synchronized, and these four timings comprise one bus cycle. At this time, the EXU performs the input of a data signal G (e.g., data input from external equipment) through the first bus (D0 through D7) at the timing T3. On the other hand, the EXU performs the output of a data signal H (e.g., data output with respect to external equipment) between timings T1 and T4.
The outputs of an address signal E (e.g., high-order address signals A8 through A15) and an address signal F (e.g., low-order address signals A0 through A7) are performed between timings T1-T4 through the second bus (A0 through A7) and the third bus (A8 through A15).
Additionally, the address signals E and F indicate the timing at which an address signal is output to the address signal terminals. Between timings T1 and T4, an address signal having a 16-bit width is output onto the second bus (A0 through A7) and the third bus (A8 through A15). The address signal, as it is, is output to the address signal terminals.
On the other hand, when a data signal is input and output, the data of an address specified by the address signal is input and output to the first bus (D0 through D7) from the external equipment connected to the data signal terminal. That is, a data G indicates the timing at which data is input from the data signal terminal to the bus control unit, and at timing T3, a data signal is input. Additionally, a data H indicates the timing at which data is output from the data signal terminal to the external equipment connected thereto, and between timings T1 and T4, a data signal is output.
A second conventional data processor includes a multiplex bus interface circuit and will be described below.
First, an EXU, a first bus (D0 through D7), a second bus (A0 through A7) 7, a third bus (A8 through A15), and an address signal terminal are the same as those described above, and for brevity such elements will not be discussed in detail. In a BCU of the data processor including the multiplex bus interface circuit, the first and second buses are connected together to the EXU. Accordingly, a total number of connecting lines between the BCU and an external device are less than the separate bus interface.
An Address Strobe (ASTB) signal, is output from the EXU, and is sent from an ASTB terminal which is an external terminal of the data processor to external equipment.
When the ASTB signal has a logic "1" level (e.g., a "high" level), it indicates the timing at which an address signal is output to a combined AD terminal (e.g., a combined address-signal and data-signal terminal). When the ASTB signal has a logic "0" level (e.g., a "low" level), it indicates the timing at which a data signal is input and output to the combined AD terminal.
The ASTB signal is input as a selection control signal to a selector which selects a data signal and a low-order address signal (A0 through A7). The selector connects the second bus (A0 through A7) to the combined AD terminal when the ASTB signal has a logic "1" level, and it connects the first bus (D0 through D7) to the combined AD terminal when the ASTB signal has a logic "0" level.
Hereinbelow, the operation of the conventional data processor including the multiplex-type I/O interface is described (as shown FIG. 2).
First, the time intervals T1-T4 indicate the timing of a clock (A) with which the data processor is synchronized, and these four timings form one bus cycle. The EXU inputs a data signal through the first bus (D0 through D7) at timing T3, and also outputs a data signal between timings T2 and T4. The output of an address signal, on the other hand, is performed between timings T1 and T4 through the second bus (A0 through A7) and the third bus (A8 through A15).
Additionally, a signal B is the timing of the combined AD terminal at the time of data input and C is the timing of the combined AD terminal at the time of data output. A signal D is an ASTB signal, which goes to a logic "1" level (e.g., a high level) at timing T1. Also, E is the timing of a signal of an address signal terminal, and the address signal terminal outputs the higher order 8 bits of the address signal between the timings T1 and T4.
If the ASTB signal first goes to a logic "1" level at timing T1, the combined AD terminal will be connected to the second bus (A0 through A7). Therefore, the lower order 8-bits signal of the address signal is output to the combined AD terminal.
Next, the ASTB signal is a logic "0" level (e.g., a low level) between timings T2 and T4, so the combined AD terminal is connected to the first bus (D0 through D7). The input of a data signal is performed at timing T3, and the output of the data signal is performed between timings T2 and T4. Additionally, the external equipment, connected to the data processor, is notified based on the level of the signal of the ASTB signal whether the signal, output to the combined AD terminal, is an address signal or a data signal.
As described above, the conventional data processor is fixed to either a separate bus interface or a multiplex bus interface. Therefore, when a system including both external equipment with a separate bus interface and external equipment with a multiplex bus interface is constructed with a single data processor, the external equipment must be connected between the data processor through a bus conversion circuit which synthesizes (e.g., multiplexes or selects between) an address signal and a data signal.
Likewise, if the data processor has only a multiplex bus interface, external equipment with a separate bus interface must be connected between data processors through a bus conversion circuit which separates an address signal and a data signal.
Thus, the conventional separate-type bus interface cannot be connected directly to external equipment having a multiplex-type bus interface. Additionally, the conventional multiplex bus interface cannot be connected directly to external equipment having a separate bus interface.
Attempts have been made at providing a combined system for separate-type bus and a multiplex-type bus systems. However, these systems have various problems.
For example, as shown in FIG. 1, Japanese Patent Application Laid-Open No. 2-176959 discloses a bus selection circuit for both a separate-type bus control method and a multiplex-type bus control method.
Similarly to the conventional systems described above, the bus selection circuit includes a bus control unit (BCU) 1, an execute (execution) unit (EXU) 2, a data bus 3 for lower data bits (D0-D7), data bus 4 for upper data bits (D8-D15), an address bus 5 for lower address bits (A0-A7), an address bus 6 for upper address bits (A8-A19), an ASTB Terminal 15, a Data Signal Terminal 16, a Combined AD Terminal 17, and an Address Signal Terminal 18. Further, this bus control unit includes a flip-flop 7 for providing an output to an AND gate 10 and a NOR gate 11, as shown in FIG. 1.
This bus selection circuit is capable of switching between a separate bus interface and a multiplex bus interface, and is functional with bus interfaces of both types of interfaces with a single data processor by switching the separate bus interface and the multiplex bus interface with a value set in the flip-flop 7.
To switch the separate/multiplex control method, the execution unit 2 sets the flip-flop 7 to level 1 for a separate bus control system, or resets the flip-flop 7 to level 0 for a multiplex bus control system. The output signal of the flip-flop 7 is input as a selection signal to a selector (including the AND gate 10 and selector 13) for data signal selection (e.g., selection of the high-order-side data signal 4 and the low-order-side data signal 3), and to a selector (including NOR gate 11 and selector 14) for selecting a low-order-side address signal 5 and a high-order-side data signal 4 through a predetermined gate circuit.
Specifically, the AND gate 10 inputs an SB/MB signal 8 and an HB/LB signal 9 and controls the selector 13. The NOR gate 11 inputs the SB/MB signal 8 and the ASTB signal 12 and controls the selector 14 and the bus size of the data signal is varied without increasing the number of terminals to achieve the multiplex bus control system and separate bus control system by one microprocessor.
For example, when a separate-type I/O interface is to be connected, the flip-flop 7 is set, in accordance with the timing diagram shown in the left-hand portion of FIG. 2. Conversely, when a multiplex-type I/O interface is to be connected, the flip-flop 7 is reset in accordance with the right-hand side of FIG. 2.
However, while the bus selection circuit disclosed in the aforementioned Japanese Patent Application Laid-Open No. 2-176959 can be connected to both external equipment with a separate bus interface and external equipment with a multiplex bus interface by switching the separate bus interface and the multiplex bus interface, a full bus cycle (e.g., four clocks T1-T4 and designated as "X" in FIG. 2) is required to switch between the separate-type bus interface and the multiplex-type bus interface and vice versa. Thus, no read or write can occur during the bus cycle, and hence no read or write can be externally output. Thus, the switching operation is slow and switching from one type of bus interface to another (e.g., separate-type to multiplex-type) is cumbersome.
Therefore, the bus selection circuit is not connected to the separate-type bus interface and the multiplex-type bus interface simultaneously.
Additionally, a flip-flop is necessary, and the flip-flop must be set and reset each time the switching from one type of interface to another. Thus, the conventional structure becomes large and inefficient. SUMMARY OF THE INVENTION
In view of the foregoing problems of the conventional systems, it is an object of the present invention to provide a data processor for controlling both a separate bus interface and a multiplex bus interface simultaneously, by sharing a terminal which outputs an address signal and a data signal and inputting and outputting the signals in a time-division manner.
Another object is provide a data processor for controlling both a separate bus interface and a multiplex bus interface simultaneously, and in which no bus cycles are lost due to switching between one type of interface to another.
Yet another object is to provide a data processor for controlling both a separate bus interface and a multiplex bus interface simultaneously, and which is not unduly large and complex.
To achieve the aforementioned objects, in a first aspect, the present invention provides a data processor in which address output timing and data input/output timing differ and which has an address signal terminal and a data signal terminal. The data processor includes a selector for selecting and outputting a data signal and part of an address signal, a combined address-and-data terminal connected to the output of the selector, wherein, when the selector selects the address signal, the selector outputs a first portion of an address field on the combined address-and-data terminal, and a first address terminal for outputting the first portion of the address field on a continuous basis, and a second address terminal for outputting a second portion of the address field on a continuous basis.
In a second aspect of the present invention, a bus control unit for connection to devices having both dedicated address terminals and multiplexed address/data terminals, is provided which includes a selector, a first address bus comprising a first field of an address and being connected to said selector, a data bus connected to the selector, a strobe signal generator for issuing a strobe signal and for selecting one of the data bus and the first address bus with the strobe signal, a first output terminal for outputting a signal on the selected one of the data bus and the first address bus, a first dedicated address output terminal, selectively coupled to the first address bus by the selector, for outputting the first field of the address, and a second data bus comprising a second field of the address being coupled to a second dedicated address output terminal for outputting the second field of the address.
In a third aspect, a processor system, includes an execution unit, and a bus control unit for receiving inputs from the execution unit, the bus control unit including a bus interface for selectively coupling the bus control unit to a peripheral including a separate-type input/output (I/O) bus interface, and for selectively coupling the bus control unit to a peripheral including a multiplex-type I/O bus interface.
In the present invention, the data processor may be equipped with a device for inhibiting, in the selector, selection of part of the address signal or the data signal. The selector may connect the data signal to the combined address and data terminal when the selection is inhibited.
With the above arrangement, the present invention allows simultaneous connection of external equipment provided with a separate bus interface and external equipment provided with a multiplex bus interface, and provides a data processor for controlling both a separate bus interface and a multiplex bus interface simultaneously, and in which no bus cycles are lost due to switching between one type of interface to another.